1. Field of the Invention
The present invention relates to a semiconductor memory device and in particular to a connecting structure of a deep trench capacitor in a memory device and a fabrication method thereof.
2. Description of the Related Art
In the rapidly evolving integrated circuit industry, the developmental trend is toward high performance, miniaturization, and high operating speeds. Accordingly, dynamic random access memory (DRAM) fabrication methods have developed rapidly. In particular, an increase of large memory capacity is important for DRAMs. Typically, DRAM cells include a transistor and a capacitor. With DRAM capacity reaching 512 MB, the size of memory cells and transistors have shrunk to meet demands for higher integration, higher memory capacity and higher operating speeds. For conventional planar capacitor technology however, relatively more useable surface area on an integrated circuit is required, thus making it difficult to meet the previously mentioned demands. Accordingly, three dimensional (3-D) technology, such as deep trench capacitor technology, has been applied to DRAM fabrication with the goal of reducing the area occupied by the transistor and the capacitor on the semiconductor substrate.
Nevertheless, as transistor size decreases, buried straps (BS), which serve as a portion of the transistor drain region and electrically connects the vertical transistors and the trench capacitors, between neighboring trenches may merge. This is called BS merge. The buried strap is formed by the thermal diffusion of high ion concentrations doped in a conductive layer in the memory cell into the substrate. This is called BS out-diffusion. If the diffusion area of the buried strap is excessive, the merging of buried straps between neighboring trenches may result, inducing short circuiting of the semiconductor memory device.
In order to prevent short circuiting of the semiconductor memory device, a trench device with a single sided buried strap has been developed to eliminate BS merge. The active area of the transistor, however, must be reduced as the memory cell density is increased. As a result, the out-diffusion of the single side buried strap may induce short channel effect and increase the contact resistance between the transistor drain region and the single side buried strap. Thus, the current and threshold voltage of the transistor are reduced, thereby reducing the memory device performance.